Level shifter with reduced static power consumption
US11705891B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2022 |
| Grant date | Jul 18, 2023 |
| Priority date | — |
| Expiry date | May 17, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356182
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide a level shifter, including: first and second NMOS transistors, wherein the sources of the first and second NMOS transistors are coupled to a first voltage, the gate of the first NMOS transistor is connected to an inverse of an input signal that varies between a second voltage and a third voltage, and wherein the gate of the second NMOS transistor receives a buffer of the input signal. a breakdown protection circuit has third and fourth NMOS transistors, the gates of the third and fourth NMOS transistors being connected to the third voltage, the drain of the first NMOS transistor being connected to the source of the third NMOS transistor, and the drain of the second NMOS transistor being connected to the source of the fourth NMOS transistor. A pull-up circuit is connected to the drains of the third and fourth NMOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.