Adaptive switch biasing scheme for digital-to-analog converter (DAC) performance enhancement
US11705921B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2021 |
| Grant date | Jul 18, 2023 |
| Priority date | — |
| Expiry date | Jan 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for adaptively generating a reference voltage (VREF) for biasing a switch driver and corresponding switch in a digital-to-analog converter (DAC). The adaptive biasing scheme may be capable of tracking process, voltage, and temperature (PVT) of the DAC. An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a switch coupled in series with the current source, and a switch driver coupled to a control input of the switch, the switch driver being configured to receive power from a first power supply rail referenced to a reference potential node; a regulation circuit comprising a first transistor coupled between the reference potential node for the DAC and the switch driver in at least one of the plurality of DAC cells; and a VREF generation circuit coupled to the regulation circuit and configured to adaptively generate a VREF for the regulation circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.