Clock synchronization loop
US11706014B1 · kind B1 · utility
1Cited by
55References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2022 |
| Grant date | Jul 18, 2023 |
| Priority date | — |
| Expiry date | Jan 20, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0679
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.