Display device having side surface connection pads
US11706956B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2020 |
| Grant date | Jul 18, 2023 |
| Priority date | — |
| Expiry date | Oct 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/32225
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A display device with a reduced area of dead spaces and a low defect occurrence rate includes a substrate including a display area and a peripheral area; and a first insulating layer disposed over the peripheral area and including a first side surface portion, a second side surface portion, and at least one recess portion. The first side surface portion includes a side surface aligned with a side surface of the substrate, and the second side surface portion includes a side surface aligned with the side surface of the substrate and is spaced apart from the first side surface portion. A first pad is disposed on the first insulating layer, extends to an edge of the substrate, fills the at least one recess portion, and includes a front end surface aligned with the side surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.