Anti-congestion flow control for reconfigurable processors
US11709664B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2020 |
| Grant date | Jul 25, 2023 |
| Priority date | — |
| Expiry date | Sep 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/825
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compiler configured to configure memory nodes with a ready-to-read credit counter and a write credit counter. The ready-to-read credit counter of a particular upstream memory node initialized with as many read credits as a buffer depth of a corresponding downstream memory node. The ready-to-read credit counter configured to decrement when a buffer data unit is written by the particular upstream memory node into the corresponding downstream memory node, and to increment when the particular upstream memory node receives from the corresponding downstream memory node a read ready token. The write credit counter of the particular upstream memory node initialized with one or more write credits and configured to decrement when the particular upstream memory node begins writing the buffer data unit into the corresponding downstream memory node, and to increment when the particular upstream memory node receives from the corresponding downstream memory node a write done token.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.