Methods and systems for a stripe mode cache pool
US11709776B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 29, 2021 |
| Grant date | Jul 25, 2023 |
| Priority date | — |
| Expiry date | Mar 29, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
N-way associative cache pools can be implemented in an N-way associative cache. Different cache pools can be indicated by pool values. Different processes running on a computer can use different cache pools. An N-way associative cache circuit can be configured to have one or more stripe mode cache pools that are N-way associative. A cache control circuit can receive a physical address for a memory location and can interpret the physical address as fields including a tag field that contains a tag value and a set field that contains a set value. The physical address can also be used to determine a pool value that identifies one of the stripe mode cache pools. A set of N cache entries in the one of the stripe mode cache pools can be concurrently searched for the tag value. The set of N cache entries is determined using the set value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.