Enhanced coverage convergence and test status during simulation runtime
US11709982B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2021 |
| Grant date | Jul 25, 2023 |
| Priority date | — |
| Expiry date | Sep 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/588
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention pertains to a method of verifying a design of an integrated circuit. The methods executes an iteration of simulation test cycle using a digital representation of the design. Next, the method obtains simulation results from the iteration of the simulation test cycle and calculates, during the simulation test cycle, a test coverage value associated with the simulation results of the iteration of the simulation test cycle. If the test coverage value is less than a target value, the method determines if the simulation test cycle fails to satisfies an iteration limiting metric. If the simulation test cycle satisfies the iteration limiting metric, the method, dynamically adjusts one or more simulation test cycle parameter during the simulation test cycle and iterates the simulation test cycle and recalculating the test coverage value until the test coverage value is at least the target value or the simulation test cycle fails to satisfy the iteration limiting metric. The method then out puts a result of the verification of the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.