Integrated circuit provided with decoys against reverse engineering and corresponding fabrication process
US11710711B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2021 |
| Grant date | Jul 25, 2023 |
| Priority date | — |
| Expiry date | Aug 6, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.