Semiconductor device including interface layer and method of fabricating thereof
US11710779B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2021 |
| Grant date | Jul 25, 2023 |
| Priority date | — |
| Expiry date | May 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device is provided that includes a first fin structure and a second fin structure extending from a substrate. The first fin structure is a first composition, and includes rounded corners. The second fin structure is a second composition, different than the first composition. A first interface layer is formed directly on the first fin structure including the rounded corners and a second interface layer directly on the second fin structure. The first interface layer is an oxide of the first composition and the second interface layer is an oxide of the second composition. A gate dielectric layer is formed over the first interface layer and the second interface layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.