Buffer cascade
US11711073B1 · kind B1 · utility
0Cited by
12References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 4, 2022 |
| Grant date | Jul 25, 2023 |
| Priority date | — |
| Expiry date | Mar 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/6871
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal conditioning circuit to reduce detrimental effects of analog circuit elements. The techniques described herein provide a cascade of buffer circuits and signal processing circuitry to measure and cancel the distortion introduced by the buffer circuits. Thus, a buffer can be added to the signal path of an input signal without the detrimental effects, such as added distortion, that typically accompany the addition of buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.