Analog-to-digital converter and clock generation circuit thereof
US11711088B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2019 |
| Grant date | Jul 25, 2023 |
| Priority date | — |
| Expiry date | May 15, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter and a clock generation circuit thereof are provided. The clock generation circuit comprises cascaded clock generation modules. The clock generation module at each stage is configured to generate a corresponding internal clock signal, and each stage of the clock generation module comprises a delay module and a logic gate module. The second input end of the N-th stage of the logic gate module is connected to the output end of the previous stage of the logic gate module, and the output end of the logic gate module is configured to output an internal clock, so that each stage of the clock generation module can generate one internal clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.