Reduction of power-over-data-lines (PODL) filter parasitics for multi-gigabit ethernet
US11711225B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2021 |
| Grant date | Jul 25, 2023 |
| Priority date | — |
| Expiry date | Oct 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H7/06
- WIPO fieldTransport
- WIPO sectorMechanical engineering
Abstract
An apparatus for filtering an electrical power signal in an Ethernet communication system includes a link interface, a power interface, and a filter connected between the link interface and the power interface. The link interface is configured to connect to an Ethernet link. The power interface is configured to connect to one or both of (i) a power-supply that supplies the electrical power signal for transfer over the Ethernet link, and (ii) a circuit that consumes the electrical power signal transferred over the Ethernet link. The filter includes at least (i) a primary inductor configured to filter the electrical power signal transferred to or from the Ethernet link, and (ii) one or more complementary inductors connected in series with the primary inductor, the one or more complementary inductors configured to reduce a parasitic capacitance of the filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.