Three-dimensional semiconductor memory devices
US11711920B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2020 |
| Grant date | Jul 25, 2023 |
| Priority date | — |
| Expiry date | Sep 14, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a substrate with a cell array region and a connection region, an electrode structure including electrodes stacked on the substrate and having a staircase structure on the connection region, a vertical channel structure on the cell array region to penetrate the electrode structure and electrically connected to the substrate, a dummy structure on the connection region to penetrate the staircase structure, and a first sidewall oxide pattern interposed between the substrate and the dummy structure. The dummy structure includes an upper portion that is on the substrate, a middle portion that is in contact with the first sidewall oxide pattern, and a lower portion that is below the middle portion. With increasing vertical distance from the upper portion, a diameter of the middle portion decreases until it reaches its smallest value and then increases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.