Indicating a probing target for a fabricated electronic circuit
US11714121B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 8, 2021 |
| Grant date | Aug 1, 2023 |
| Priority date | — |
| Expiry date | Jul 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for indicating a probing target for a fabricated electronic circuit including: generating an electronic, three-dimensional model based on manufacturing layout information of a fabricated circuit; obtaining, with a vision system, visual environment information for the fabricated circuit; scaling and orienting the three-dimensional model by a scaler and mapper based on the visual environment information; overlaying the three-dimensional model with the visual environment information to produce a correlated image; obtaining an identification of a desired network node of the fabricated circuit; and indicating a probing target, the probing target corresponding to the desired network node of the fabricated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.