Predictive memory management
US11714558B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 11, 2021 |
| Grant date | Aug 1, 2023 |
| Priority date | — |
| Expiry date | Oct 11, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods related to predictive memory management are described. Error correction operations can be performed on a memory system and can include a latency associated with performing various error correction techniques on data and the health of physical addresses used to store the data can be predicted based on that latency information. In an example, a method can include determining, by a controller, latency information corresponding to one or more error correction operations performed on data received by the controller, and assigning, based on the latency information corresponding to a health of physical address locations corresponding to the data, and taking an action involving the physical address locations based, at least in part, on the information corresponding to the health of the plurality of physical address locations corresponding to the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.