Fine-grained pipelining using index space mapping
US11714653B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2021 |
| Grant date | Aug 1, 2023 |
| Priority date | — |
| Expiry date | Mar 20, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/5017
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for computing includes defining a processing pipeline, including at least a first stage in which producer processors compute and output data to respective locations in a buffer and a second processing stage in which one or more consumer processors read the data from the buffer and apply a computational task to the data read from the buffer. The computational task is broken into multiple, independent work units, for application by the consumer processors to respective ranges of the data in the buffer, and respective indexes are assigned to the work units in a predefined index space. A mapping is generated between the index space and the addresses in the buffer, and execution of the work units is scheduled such that at least one of the work units can begin execution before all the producer processors have completed the first processing stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.