Stuck-at fault mitigation method for ReRAM-based deep learning accelerators
US11714727B2 · kind B2 · utility
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Key dates
| Filing date | Jan 21, 2022 |
| Grant date | Aug 1, 2023 |
| Priority date | — |
| Expiry date | Jan 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A stuck-at fault mitigation method for resistive random access memory (ReRAM)-based deep learning accelerators, includes: confirming a distorted output value (Y0) due to a stuck-at fault (SAF) by using a correction data set in a pre-trained deep learning network, by means of ReRAM-based deep learning accelerator hardware; updating an average (μ) and a standard deviation (σ) of a batch normalization (BN) layer by using the distorted output value (Y0), by means of the ReRAM-based deep learning accelerator hardware; folding the batch normalization (BN) layer in which the average (μ) and the standard deviation (σ) are updated into a convolution layer or a fully-connected layer, by means of the ReRAM-based deep learning accelerator hardware; and deriving a normal output value (Y1) by using the deep learning network in which the batch normalization (BN) layer is folded, by means of the ReRAM-based deep learning accelerator hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.