Unit for a bus system, master-slave bus system with a plurality of units, and method for addressing units of a bus system
US11714768B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2021 |
| Grant date | Aug 1, 2023 |
| Priority date | — |
| Expiry date | Jan 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/40013
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The disclosure relates to a unit for a bus system, a master/slave bus system with such units, and a method for assigning individual unit addresses for units of a bus system, wherein through the use of an enable signal, which is relayed from unit to unit, only one unit is respectively in an allocation mode in which the unit that is respectively in the allocation mode is allocated an individual unit address so that the units of the bus system can each be allocated with the unique individual address one after the other in the sequence of their cabling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.