Serial FFT-based low-power MFCC speech feature extraction circuit
US11715456B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2020 |
| Grant date | Aug 1, 2023 |
| Priority date | — |
| Expiry date | May 12, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG10L25/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
It discloses a serial FFT-based low-power MFCC speech feature extraction circuit, and belongs to the technical field of calculation, reckoning or counting. The circuit is oriented toward the field of intelligence, and is adapted to a hardware circuit design by optimizing an MFCC algorithm, and a serial FFT algorithm and an approximation operation on a multiplication are fully used, thereby greatly reducing a circuit area and power. The entire circuit includes a preprocessing module, a framing and windowing module, an FFT module, a Mel filtration module, and a logarithm and DCT module. The improved FFT algorithm uses a serial pipeline manner to process data, and a time of an audio frame is effectively utilized, thereby reducing a storage area and operation frequency of the circuit under the condition of meeting an output requirement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.