Method for packaging integrated circuit chip
US11715644B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2021 |
| Grant date | Aug 1, 2023 |
| Priority date | — |
| Expiry date | Dec 11, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for packaging an integrated circuit chip includes the steps of: a) providing a plurality of dies and a lead frame which includes a plurality of bonding parts each having a die pad, a plurality of leads each having an end region disposed on and connected to the die pad, and a plurality of bumps each disposed on the end region of a respective one of the leads; b) transferring each of the dies to the die pad of a respective one of the bonding parts to permit each of the dies to be flipped on the respective bonding part; and c) hot pressing each of the dies and the die pad of a respective one of the bonding parts to permit each of the dies to be bonded to the bumps of the respective bonding part.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.