Barrier structure configured to increase performance of III-V devices

US11715792B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Yun-Hsiang Wang · Hsinchu, TW
• Chun Lin Tsai · Baoshan, TW
• Jiun-Lei Jerry Yu · Dashulong, TW
• Po-Chih Chen · Hsinchu, TW
• Chia-Ling Yeh · Hsinchu, TW
• Ching-Yu Chen · Keelung, TW

Key dates

• Filing date: May 12, 2020
• Grant date: Aug 1, 2023
• Expiry date: Apr 10, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/343

Abstract

Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.