Chip with pad tracking
US11716073B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2022 |
| Grant date | Aug 1, 2023 |
| Priority date | — |
| Expiry date | Jan 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018592
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A chip with pad tracking having an input/output buffer (I/O buffer), a pad, and a bias circuit. The I/O buffer is powered by a first power and is coupled to the pad. The pad is coupled to the system power. The bias circuit generates a bias signal to be transferred to the I/O buffer to block a leakage path within the I/O buffer when the system power is on and the first power is off. The bias circuit is a voltage divider which generates a divided voltage as the bias signal. In an example, the bias circuit is powered by a second power that is independent from the first power and is not drawn from the pad. In another example, a power terminal of the bias circuit is coupled to an electrostatic discharging bus, and the pad is coupled to the electrostatic discharging bus through a diode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.