Patent · US Active

Calibration loop for differential sub-sampling phase detector in sub-sampling phase locked loop

US11716087B1 · kind B1 · utility

0Cited by

7References

20Claims

0Family size

Assignee

Cisco Technology, Inc. · US

Inventors

Abhishek Bhat · Weilersville, US
Romesh Kumar Nandwana · Urbana, US

Key dates

Filing date	Jan 24, 2022
Grant date	Aug 1, 2023
Priority date	—
Expiry date	Jan 24, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/0992
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Presented herein are techniques for implementing a differential sub-sampling phase locked loop (PLL). A method includes detecting a common-mode voltage on an output of a differential sub-sampling phase detector operating in the differential sub-sampling phase locked loop, and controlling, based on the common-mode voltage, a duty cycle of a feedback signal of the differential sub-sampling phase locked loop that is fed back to the differential sub-sampling phase detector.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.