Semiconductor devices
US11716839B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2021 |
| Grant date | Aug 1, 2023 |
| Priority date | — |
| Expiry date | Aug 20, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
Abstract
A semiconductor device includes an active pattern on a substrate, a gate structure buried at an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure covering a lower sidewall of the bit line structure, a contact plug structure on the active pattern and adjacent to the bit line structure, and a capacitor on the contact plug structure. The lower spacer structure includes first and second lower spacers that are sequentially stacked from the lower sidewall of the bit line structure in a horizontal direction that is substantially parallel to an upper surface of the substrate, the first lower spacer includes an oxide, and contacts the lower sidewall of the bit line structure, but does not contact the contact plug structure, and the second lower spacer includes a material different from any of the materials of the first lower spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.