Method and apparatus for compressing and decompressing sparse data sets
US11720252B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2022 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Mar 4, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/0495
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure include a digital circuit and method for multi-stage compression. Digital data values are compressed using a multi-stage compression algorithm and stored in a memory. A decompression circuit receives the values and performs a partial decompression. The partially compressed values are provided to a processor, which performs the final decompression. In one embodiment, a vector of N length compressed values are decompressed using a first bit mask into two N length sets having non-zero values. The two N length sets are further decompressed using two M length bit masks into M length sparse vectors, each having non-zero values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.