Path prediction method used for instruction cache, access control unit, and instruction processing apparatus
US11720365B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2020 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Dec 9, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction processing apparatus is disclosed and includes: an instruction cache, which maps data blocks in a memory based on a multi-way set-associative structure and includes a plurality of cache lines; and an access control unit, coupled between an instruction fetch unit and the instruction cache, and adapted to read the plurality of cache lines respectively by using a plurality of data channels, and select a hit cache line from the plurality of cache lines by using a plurality of selection channels, to obtain an instruction, where the access control unit includes a path prediction unit, where the path prediction unit obtains, based on a type of the instruction, path prediction information corresponding to an instruction address, and enables at least one data channel and/or at least one selection channel based on the path prediction information. The instruction processing apparatus selectively enables an access channel of the instruction cache based on the path prediction information by using the access control unit, to reduce dynamic power consumption in access. A corresponding path prediction method, a computer system, and a system-on-chip are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.