Error containment for enabling local checkpoint and recovery
US11720440B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2021 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Aug 14, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments include a parallel processing computer system that detects memory errors as a memory client loads data from memory and disables the memory client from storing data to memory, thereby reducing the likelihood that the memory error propagates to other memory clients. The memory client initiates a stall sequence, while other memory clients continue to execute instructions and the memory continues to service memory load and store operations. When a memory error is detected, a specific bit pattern is stored in conjunction with the data associated with the memory error. When the data is copied from one memory to another memory, the specific bit pattern is also copied, in order to identify the data as having a memory error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.