Semiconductor device and method for controlling plural chips
US11720513B2 · kind B2 · utility
0Cited by
8References
20Claims
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Key dates
| Filing date | Sep 1, 2022 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Sep 1, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first chip, a plurality of second chips, and a plurality of first signal lines. The first chip is electrically connected to a terminal group that receives a first signal from a host. The second chips are electrically connected to the first chip and are capable of outputting respective ready/busy signals. The ready/busy signals can be transferred through the first signal lines. Each of the second chips is respectively connected to the first chip through a corresponding first signal line among the plurality of first signal lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.