Shift register circuit and driving method thereof, gate driver and display panel
US11721289B2 · kind B2 · utility
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19Claims
0Family size
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Key dates
| Filing date | Mar 9, 2021 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | May 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/12
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shift register circuit (100) includes: an input circuit (110), a reset circuit (180), a first control circuit (120), a second control circuit (130), a third control circuit (140), a fourth control circuit (150), a fifth control circuit (160), a first output circuit (170a), a second output circuit (170b) and a third output circuit (170c). The shift register circuit (100) is configured to be capable of providing three different output signals as three different gate driving signals required to drive a pixel array of a display panel (810).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.