Memory device capable of outputting fail data in parallel bit test and memory system including the memory device
US11721408B2 · kind B2 · utility
2Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Jul 29, 2021 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Oct 5, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array and a test controller. The memory cell array includes a plurality of memory cells, where the memory cell array is divided into multiple regions. The test controller is configured to perform a parallel bit test (PBT) on the plurality of memory cells, where the test controller selects fail data including a fail data bit among internal data output from the multiple regions during the PBT, and outputs the fail data via a data input/output signal line to the outside of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.