Copper-bonded memory stacks with copper-bonded interconnection memory systems
US11721685B2 · kind B2 · utility
1Cited by
4References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 26, 2021 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Aug 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory stack including a number of memory dies interconnected via copper bonding, a logic die coupled to the memory stack via a copper bonding. The memory system further includes a buffer die extended to provide the copper bonding between the logic die and the memory stack and a silicon carrier layer bonded to the memory stack and the logic die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.