Vertical solid-state devices
US11721797B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 19, 2021 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Oct 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H29/142
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
As the pixel density of optoelectronic devices becomes higher, and the size of the optoelectronic devices becomes smaller, the problem of isolating the individual micro devices becomes more difficult. A method of fabricating an optoelectronic device, which includes an array of micro devices, comprises: forming a device layer structure including a monolithic active layer on a substrate; forming an array of first contacts on the device layer structure defining the array of micro devices; mounting the array of first contacts to a backplane comprising a driving circuit which controls the current flowing into the array of micro devices; removing the substrate; and forming an array of second contacts corresponding to the array of first contacts with a barrier between each second contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.