Pulse width modulation clock synchronization
US11722089B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2022 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Nov 16, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02T10/72
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A controller includes a first processor for a first power inverter. Computer-readable media is configured to store computer-executable instructions configured to cause the first processor to: generate a first clock signal and a second clock signal; identify a pulse width modulation method of the first power inverter and a pulse width modulation method of a second power inverter; identify and compare a switching frequency of the first power inverter and a switching frequency of the second power inverter; determine an optimized phase shift between the first power inverter and the second power inverter responsive to the pulse width modulation method of the first power inverter and the pulse width modulation method of the second power inverter and the switching frequency of the first power inverter and the switching frequency of the second power inverter; and synchronize the optimized phase shift between the first power inverter and the second power inverter. A second processor for the second power inverter is configured to receive the second clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.