Device and method for low-latency and encrypted hardware layer communication
US11722291B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2021 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Sep 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method of low-latency and encrypted hardware layer communication includes calculating, by an encryption circuit of a communication bridge controller, a pre-calculated encryption keys corresponding to a block encryptor of the encryption circuit, each block encryptor configured to use a corresponding pre-calculated encryption key to encrypt a corresponding unencrypted data block of a data transmission having one or more unencrypted data blocks, storing the one or more pre-calculated encryption keys in an encryption key memory associated with the communication bridge, for each unecrypted data block, encrypting the unencrypted data block using the corresponding pre-calculated encryption key to generate an encrypted data block and an authentication code block for the unencrypted data block, aggregating one or more encrypted data blocks into an encrypted data transmission, and generating an authenticated code corresponding to the encrypted data transmission based upon each of the authentication code blocks of each of the encrypted data blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.