Integrated circuit read only memory (ROM) structure
US11723194B2 · kind B2 · utility
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4References
20Claims
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Key dates
| Filing date | Mar 5, 2021 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Mar 5, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5286
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit read only memory (ROM) structure includes a first ROM transistor with a first gate electrode, a first source, and a first drain, and a second ROM transistor with a second gate electrode, a second source, and a second drain. A drain conductive line is over the first drain and the second drain, and is between the first drain and the second drain. The first drain, the drain conductive line and the second drain are between the first gate electrode and the second gate electrode, and a first trench isolation structure electrically isolates the first drain from the first source is below the first gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.