Memory extension with error correction
US11726665B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2021 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Aug 27, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for encoding additional data in a memory without requiring an increase to the physical storage capacity of the memory device are described. Additional data can be encoded with error correction code symbols without having to physically store the additional data in memory, while retaining the number of error correction code bits used by the memory. When data is read from memory without the additional data, erasure decoding can be performed to recover the additional data. When errors are encountered in the data read from memory, the errors can be treated as erasures for different predictions of the error locations to determine if the errors can be corrected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.