FPGA acceleration system for MSR codes
US11726876B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2021 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Jul 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.