Multiple block error correction in an information handling system
US11726879B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2021 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Aug 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information handling system includes a first memory and a baseboard management controller. The first memory stores a first firmware partition and a second firmware partition. The baseboard management controller includes a second memory. The baseboard management controller begins execution of a DM-Verity daemon, and performs periodic patrol reads of the first firmware partition. The baseboard management controller detects one or more block failures in the first firmware partition, and stores information associated with the one or more block failures in a message box of the second memory. In response to the entire first firmware partition being scanned, the baseboard management controller switches a boot partition from the first firmware partition to the second firmware partition, and initiates a reboot of the information handling system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.