Tag processing for external caches
US11726920B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2019 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Sep 12, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a cache memory and a memory controller coupled to the cache memory. The memory controller is configured to receive a first read request from a cache controller over an interconnect, the first read request comprising first tag data identifying a first cache line in the cache memory, and determine that the first read request comprises a tag read request. The memory controller is further configured to read second tag data corresponding to the tag read request from the cache memory, compare the second tag data read from the cache memory to the first tag data received from the cache controller with the first read request, and if the second tag data matches the first tag data, initiate an action with respect to the first cache line in the cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.