Iterative generation of top quality plans in automated plan generation for artificial intelligence applications and the like
US11727289B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2018 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Sep 20, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for improving performance of at least one hardware processor solving a top-k planning problem includes obtaining, in a memory coupled to the at least one processor, a specification of the planning problem in a planning language; obtaining, in a first iteration carried out by the at least one processor, at least one solution to the planning problem; and modifying the planning problem, in the first iteration carried out by the at least one processor, to forbid the at least one solution. The method further includes repeating, by the at least one processor, the obtaining of the at least one solution and the modifying to forbid the at least one solution, for a plurality of additional iterations, after the first iteration, until a desired number, k, of solutions to the planning problem are found or until no further solutions exist, whichever comes first.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.