Patent · US Active

Systems and methods for detecting counterfeit or defective memory

US11728000B1 · kind B1 · utility

1Cited by
17References
18Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 13, 2021
Grant dateAug 15, 2023
Priority date
Expiry dateMay 13, 2041

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C2029/5006
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A system for testing memory includes logic that is configured to perform various normal memory operations (e.g., erase, read and write operations) on a memory device and to determine operational parameters associated with the memory operations. As an example, the amount of time to perform one or more memory operations may be measured, a number of errors resulting from the memory operations may be determined, or a number of memory cells storing noisy bits may be identified. One or more of the operational parameters may then be analyzed to determine whether they are in a range expected for counterfeit or defective memory. If so, the logic determines that the memory under test is counterfeit or defective and provides a notification about such determination.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.