Patent · US Active

Arrangement for an optoelectronic component, manufacturing process and optoelectronic component

US11728444B2 · kind B2 · utility

0Cited by
5References
18Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 2, 2021
Grant dateAug 15, 2023
Priority date
Expiry dateJan 28, 2042

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10F77/933

Abstract

An arrangement for an optoelectronic component includes a substrate and an optical semiconductor chip arranged on the substrate. The optical semiconductor chip has an optically active region, a first optically non-active region, and a second optically non-active region. A connection structure connects a chip-side electrical connection to the optically active region. An electrical connection connects the chip-side electrical connection to a second substrate-side electrical connection. A coating is provided in a layer stack in the optically active region, in the first optically non-active region, and in the second optically non-active region. The layer stack includes a first layer and a second layer arranged above the first layer. The chip-side electrical connection and the connection structure in the first optically non-active region and the protective layer in the second optically non-active region are each arranged between the first layer and the second layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.