High voltage switch with cascaded transistor topology
US11728804B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2022 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | May 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2017/6875
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switching apparatus includes three or more series-connected transistors, and it further includes a balancing network. The balancing network includes a resistor network configured to divide a voltage from a voltage source across the series-connected transistors. The resistor network includes at least two resistive legs connected in parallel. In each resistive leg, two or more resistors are connected in series. The balancing network may further comprise at least one capacitive leg of series-connected capacitors connected across the series-connected transistors, and it may further comprise at least one leg of series-connected avalanche diodes connected across the series-connected transistors for overvoltage protection. In example embodiments, the series-connected transistors are JFETs. In other example embodiments, the series-connected transistors may be HEMTs or GaN transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.