LSB dithering for segmented DACs
US11728821B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2021 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Nov 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital to analog (DAC) circuit that performs least significant bit (LSB) dithering comprises: a first DAC; an auxiliary code generator configured to produce an auxiliary code; an auxiliary DAC configured to receive the auxiliary code and convert the auxiliary code into an analog version of the auxiliary code; and summing circuitry to dither LSBs of the first DAC with the auxiliary code. The auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit, the auxiliary code has a smaller range than that of a range of binary-weighted LSBs of the main DAC and/or the auxiliary code generator is configured to produce the auxiliary code as a predetermined repeating sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.