Clock generating circuit and wireless communication device including the same
US11728961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2022 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Jan 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generating circuit includes a first frequency multiplier configured to generate a second clock signal having a second frequency based on a first clock signal having a first frequency, and a second frequency multiplier configured to generate a third clock signal having a third frequency based on the second clock signal. The first frequency multiplier includes a circuit configured to control a duty cycle of the first clock signal, a delay circuit configured to receive the duty controlled clock signal, and delay the received signal based on a duty cycle of the second clock signal to output a first delay clock signal, and an XOR gate configured to perform an XOR computation using the duty controlled clock signal and the first delay clock signal to output the second clock signal. The second frequency is greater than the first frequency, and the third frequency is greater than the second frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.