Method and apparatus for low latency charge coupled decision feedback equalization
US11729029B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2021 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Nov 12, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/065
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A mixed signal receiver includes a first sample and hold (S/H) circuit having a first S/H input terminal to receive an analog input signal and a first S/H output terminal directly coupled to a first common node; a first data slicer having a first slicer input terminal coupled to the first common node; and a first data-driven charge coupling digital-to-analog converter (DAC) including: (i) a DAC input terminal to receive a first digital signal from a first digital output of the first data slicer, (ii) a DAC output terminal directly coupled to the first common node, (iii) a plurality of capacitor modules configured to be pre-charged during a sample phase, and (iv) logic components, wherein when the logic components toggle a voltage on the plurality of capacitor modules, charge is capacitively coupled to or from the first common node during an immediately subsequent hold phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.