Digital encoding algorithm for pixelated detectors
US11729345B2 · kind B2 · utility
1Cited by
2References
19Claims
0Family size
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Key dates
| Filing date | May 29, 2020 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Dec 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N2223/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A detector for imaging and efficiently digitizing a spatial distribution of photon flux includes pixel circuits that compressively encode pixel values generated by integrated analog to digital converters (ADCs). On-pixel digital compression circuits (DCCs) implement compression to increase continuous frame rate by reducing the number of bits per pixel while keeping quantization error below Poisson noise. Several mapping algorithms for photon-counting and charge-integrating detectors and compact digital logic implementations are presented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.