Circuit board connector footprint
US11729898B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2022 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Jun 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10901
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A printed circuit board includes a layered substrate having a plurality of layers having an electrical connector footprint configured to receive an electrical connector. The printed circuit board includes pair anti-pads passing through the layered substrate around pairs of signal vias. The printed circuit board includes ground vias passing through the layered substrate. The ground vias are configured to receive ground pins of the electrical connector. The ground vias are located outside of the pair anti-pads. The printed circuit board includes SI vias passing through the layered substrate. The SI vias form an SI fence surrounding the corresponding pair anti-pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.