Method for optimized filling hole and manufacturing fine line on printed circuit board
US11729917B2 · kind B2 · utility
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11Claims
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Key dates
| Filing date | Jul 15, 2021 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Sep 8, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/054
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A method for optimized filling holes and manufacturing fine lines on a printed circuit board (PCB) carries out the two processes separately. The inner wall of the hole is metalized with reduced graphene oxide (rGO) and then electroplated to fill the hole with copper. The processes are individually performed and thus operating parameters are considered independently. As a result, the copper-plating fillings are evenly compact and the fine lines have square profiles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.