Memory array for storing odd and even data bits of data words in alternate sub-banks to reduce multi-bit error rate and related methods
US11733898B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 26, 2021 |
| Grant date | Aug 22, 2023 |
| Priority date | — |
| Expiry date | Apr 26, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array for storing odd and even data bits of data words in alternate sub-banks to reduce multi-bit error rate is disclosed. The memory array alternates odd data bits of a first plurality of data words in consecutive columns a first sub-bank of first and second memory banks and even data bits of the first plurality of data words in consecutive columns of a second sub-bank of the first and second memory banks. For example, the lowest bits of each of N data words are stored in a first N consecutive columns of a first sub-bank. The second bits of the N data words are stored in the next N consecutive columns of a second sub-bank. The N data bits in each of the bit positions of the N data words are interleaved in corresponding column mux sets. Alternating odd and even bits between sub-banks reduces multi-bit soft errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.